============================================================== Guild: wafer.space Community Channel: ๐Ÿ—๏ธ - Designing / cob Topic: Channel for discussing chip-on-board packaging options for wafer.space bare die. After: 04/30/2026 23:59 ============================================================== [05/01/2026 01:55] mithro_ Great work Mike! [05/01/2026 01:55] mithro_ From what I have seen so far, I don't think the bond house we are using will care at all. [05/01/2026 01:59] mithro_ @RebelMike / @Greg - It is very likely whatever we end up using on the TinyQV and/or Racquet die will become the standard CoB layout for the non-1x1 projects getting packaged. [05/01/2026 02:01] mithro_ @RebelMike / @Greg / @Leo Moser (mole99) - I'm also open to the alternative idea of changing the GF180MCU template I/O allocations for these sizes to make things easier. [05/01/2026 02:05] dnaltews a pin 1 marker on the silkscreen for the mezzanine connector might be nice just for completeness [05/01/2026 02:07] namibj Might wrongly suggest polarization. [05/01/2026 02:19] polyfractal just got my motherboard breakout PCBs ... i severely underestimated how small the connector pins/pads would be ๐Ÿ˜… probably should have bought a stencil to go with it, guess we'll see how good I am at fine soldering! {Reactions} ๐Ÿ’œ [05/01/2026 02:30] mithro_ Hot Air reflow and a good (pre-)heating plate helps a lot, surface tension is your friend. {Reactions} ๐Ÿ‘ [05/01/2026 03:36] anfroholic Sorry, it seems I didn't hit save before I hit commit. [05/01/2026 06:43] greg.hashtag.9468 Do you have the scripts which generated this? Would be nice to get an SVG if possible to put into the datasheet/spec for the chip [05/01/2026 06:47] greg.hashtag.9468 Was this checked in somewhere? I'm happy to take a look and poke around with the bonding for the 0p5x1 [05/01/2026 06:48] rebelmike Itโ€™s in https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev/mezzanine-0p5x1 {Embed} https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev/mezzanine-0p5x1 chip-on-board-wire-bonded-pcbs/mezzanine-0p5x1 at half-slot-dev ยท ... Wire bonded chip on board PCB designs. Contribute to MichaelBell/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub. 2026-05_media/chip-on-board-wire-bonded-pcbs-D673F {Reactions} ๐Ÿ‘ [05/01/2026 06:49] anfroholic I am told these may be partially out of date, but here you go! {Attachments} 2026-05_media/GD04_chip_top_10_8-53FBA.svg 2026-05_media/GD02_chip_top_14_4-96145.svg 2026-05_media/GD03_chip_top_6_6-B0050.svg 2026-05_media/GD04_chip_top_6_8-F78BA.svg [05/01/2026 06:51] rebelmike Ah, no it isn't - apparently I was on Andrew's branch and committed and pushed it there. I'll merge that [05/01/2026 06:53] greg.hashtag.9468 Thanks ๐Ÿ‘ [05/01/2026 06:54] rebelmike I'll also make a PR against the main repo. But possibly after I've had some coffee ๐Ÿ™‚ [05/01/2026 06:56] greg.hashtag.9468 No worries, I'll only get to looking at this in depth in a few hours [05/01/2026 07:02] mithro_ It is a super horrific AI written bit of code. Let me see if I can upload it somewhere. At some point I think I'm (or really I'm going to have a better attempt at AI doing it) going to try and write/good a proper version and integrate it into either https://platform.wafer.space or maybe even LibreLane. {Embed} https://platform.wafer.space/ Welcome to wafer.space โ€ฆ Platform for wafer.space low cost silicon manufacturing. {Reactions} ๐Ÿ’œ [05/01/2026 07:03] mithro_ @Leo Moser (mole99) / @Andrew Wingate - I just had the thought that maybe it should be LibreLane that is generating Andrew's KiCAD footprints + wire bonding diagrams and my random pin out diagrams? [05/01/2026 07:03] mithro_ @Leo Moser (mole99) - Terrible or good idea? ๐Ÿ˜› [05/01/2026 07:04] anfroholic I don't know how that would work? You must specify a standard wirebonding frame first? Like from a set? [05/01/2026 07:06] rebelmike Not sure if Librelane, but a script that could generate the correct sized pad + drawing annotations in the exact pin positions could be useful. For the whole padring I guess it would be possible at least for a standard rectangular one - just push the pins out until the 45 degree rule wasnโ€™t violated [05/01/2026 07:33] rebelmike Yeah I donโ€™t know how much thought was given to the pin allocations for the different sizes - I suspect @Leo Moser (mole99) was just trying things out. Potentially we try to route them all to match the existing template as much as possible, then change the template to make them match completely? Though I suspect in general this doesnโ€™t matter too much - the case of wanting them to match has only really come up because TinyQV was used in different slot sizes as a test. [05/01/2026 07:38] mithro_ I think having a "standard" which means people can share "motherboards" PCBs is helpful rather than everyone having to design new ones. [05/01/2026 07:42] rebelmike I donโ€™t think a standard mapping of the template pinout is required for that - itโ€™s probably the other way around: if there was a standard SoC host motherboard (with flash, ram, etc) and the pinout for that and all the breakouts was known, you could just wire things up correctly in the silicon. [05/01/2026 07:43] rebelmike But I guess that is basically the same as saying make the template match whatever we end up with [05/01/2026 07:50] anfroholic That is a good point though to think about some things upstream instead of all downstream. Thanks for the thought [05/01/2026 12:38] mithro_ @Greg - Don't say I didn't warn you ๐Ÿ˜› - https://github.com/mithro/wafer-space-die-pad-diagrams {Embed} https://github.com/mithro/wafer-space-die-pad-diagrams GitHub - mithro/wafer-space-die-pad-diagrams Contribute to mithro/wafer-space-die-pad-diagrams development by creating an account on GitHub. 2026-05_media/wafer-space-die-pad-diagrams-AC8B1 {Reactions} โค๏ธ [05/01/2026 13:42] thorben_61995 That looks much more professional than what I did ๐Ÿ˜… [05/01/2026 13:43] thorben_61995 {Attachments} 2026-05_media/IMG_20260429_145204314-A6D5C.jpg [05/01/2026 14:24] tholin {Attachments} 2026-05_media/padout-C400A.png [05/01/2026 14:26] anfroholic @Tholin here's yours, anyone else can have theirs if they wish. We're looking to integrate this into the verification system, so you'd just get one anyways. {Attachments} 2026-05_media/AS03_chip_top_6_0-B0753.png [05/01/2026 14:27] anfroholic Yours is still very neat that is shows the sub-projects as well! [05/01/2026 14:33] tholin To show the macro locations is a bit tricky. The position of each macro is specified in the librelane config, but to get its size, you need to open up its LEF. {Reactions} ๐Ÿ‘ [05/01/2026 14:34] tholin I see the analog pads are all just labeled "PAD" in this [05/01/2026 14:35] anfroholic Yeah, we were talking earlier about pincounts and what's actually needed. How many of the pins did you end up using for real? all of them? Most of them? [05/01/2026 14:40] tholin All of them {Reactions} ๐Ÿ’ฏ [05/01/2026 14:41] anfroholic Like I said we were talking about some reduced pin counts. In your opinion what's a reasonable low number? [05/01/2026 14:41] anfroholic *lower [05/01/2026 14:42] tholin I always need as many as possible for my processor designs for memory throughput {Reactions} ๐Ÿคฃ [05/01/2026 14:43] tholin I can finally build 32-bit wide data buses on wafer.space [05/01/2026 14:43] anfroholic It's all good. There really is no answer. Ah, ok, that's a good thought. [05/01/2026 14:43] tholin My GFMPW-1 RISC-V core multiplexes both halves of the address and both halves of a word onto the same 16 pins [05/01/2026 14:43] tholin 4 clock cycles for a single instruction fetch, worst case [05/01/2026 14:44] tholin 3 clock cycles best case [05/01/2026 14:44] anfroholic I see. Thanks for the insight [05/01/2026 14:45] tholin wafer.space still doesnโ€™t give enough pins for separate address and data buses on a 32-bit CPU without compromises, but its almost there {Reactions} ๐Ÿ‘ [05/01/2026 14:46] anfroholic Getcha, the question revolved around trying to come up with some less expensive cob or packaging alternatives. [05/01/2026 15:00] ravenslofty CHES uses 4 GPIOs for JTAG and 11 for ULPI {Reactions} ๐Ÿ’œ [05/01/2026 15:00] ravenslofty (if that's a useful datapoint) [05/01/2026 15:01] anfroholic They are all useful. Thank you. I think we just need to put together some numbers and see where any kind of step functions are. [05/01/2026 15:07] ravenslofty (side note, I don't suppose there's a way to manually annotate the pad diagrams with actual pin functions rather than the toplevel pin name) [05/01/2026 15:08] tholin Unfortunately, we are talking about integrated circuits, where IO is often the bottleneck [05/01/2026 15:08] anfroholic Does this data exist somewhere? If it exists and people will use it we can incorporate it into the pipeline [05/01/2026 15:09] ravenslofty ULPI was my solution to that problem :p [05/01/2026 15:09] ravenslofty uh, I have it as source code defines; nothing more structured if that's what you're asking for [05/01/2026 15:09] anfroholic Can you share what that acronym is? [05/01/2026 15:09] anfroholic I see, if there's a way to get it into the GDS that's our source of truth. [05/01/2026 15:10] ravenslofty UTMI+ Low Pin Interface; uh, USB Hi Speed PHY interface {Reactions} ๐Ÿ’œ [05/01/2026 15:10] ravenslofty which means I can do 480Mbps serial (well, theoretically) while having my chip only have to achieve 60MHz [05/01/2026 15:11] tholin I mean, particularly for memory. Ever CPU I ever taped out on gf180mcu was memory bottlenecked. Caravel was **aggressively** memory bottlenecked. [05/01/2026 15:11] anfroholic I know Tim has been interested in SerDes, this can probably help with pincounts someday as well? {Reactions} ๐Ÿ‘ ๐ŸŽ‰ [05/01/2026 15:11] ravenslofty yes [05/01/2026 15:11] anfroholic I am marginally aware how they didn't let you do a lot [05/01/2026 15:12] ravenslofty (although I feel like at that point we *need* a better standard cell library >.>) {Reactions} ๐Ÿ’ฏ [05/01/2026 15:12] ravenslofty (this is not directed at Tholin, it's directed at myself to try to get back to working on my synthesisable domino logic library) {Reactions} waferspace [05/01/2026 15:19] tholin There is a lot I need to improve about my SCL before Iโ€™m fully confident in it [05/01/2026 15:20] ravenslofty It also doesn't help that I'm having to work with custom timing extraction scripts from ngspice to characterise the cells [05/01/2026 15:23] ravenslofty I also think my library will probably have to rely on yours for the non-logic stuff because I have zero clue what to do there [05/01/2026 15:44] rebelmike Tiny Tapeout offers 26 pins (plus any analog pins) so 26-30 might be something to consider for a lower cost option on the smaller slots. Although Wafer Space is quite a different offering to TT people might prototype on TT and then bring things across. It might also be interesting to have a higher pin count option for the full size slot. {Reactions} ๐Ÿ’ฏ [05/01/2026 15:45] anfroholic I don't think there are any plans to lower any counts, only to try to offer a lower cost version. [05/01/2026 15:49] rebelmike I guess I was thinking it might be interesting to have the current option (56 IOs) plus a smaller option (~26 IOs) for the half slots. And the current option plus a larger option (~80 IOs?) on the full slot. [05/01/2026 15:52] rebelmike Though the larger option would obviously need a different connector (presumably 2x50) - I know there was some concern about two connectors but TT should soon find out if that causes any problems [05/01/2026 15:54] anfroholic 2x mezzanine was shunned pretty hard by those here, so I don't see that as an option. Maybe if we can get back to looking at some kind of LGA or something. https://discord.com/channels/1361349522684510449/1408134567491145728/1426376335709966446 [05/01/2026 15:56] rebelmike Yeah I remember that discussion but I think it was probably over cautious. But the new TT boards should be a good indicator of whether itโ€™s a problem in practice (they have 2x mezzanine) {Reactions} ๐Ÿ‘ [05/01/2026 16:05] trev5514 I was going to use this for my daughter/motherboard cards: HC-PBB40C-90DP-0.4V-02 it's a 90 pin version, much easier than a 2x50 (in my opinion). [05/01/2026 16:05] trev5514 https://jlcpcb.com/partdetail/HCTL-HC_PBB40C_90DP_0_4V02/C19089238 {Embed} https://jlcpcb.com/partdetail/HCTL-HC_PBB40C_90DP_0_4V02/C19089238 HC-PBB40C-90DP-0.4V-02 | HCTL | Board-to-Board and Backplane Connec... HC-PBB40C-90DP-0.4V-02 from HCTL - Board-to-Board and Backplane Connector is available for JLCPCB assembly, check the stock, pricing and datasheet, and let JLCPCB helps you assemble the part HC-PBB40C-90DP-0.4V-02 for free. 2026-05_media/logo-og-B75C2.png {Reactions} ๐Ÿ‘ ๐Ÿ‘€ [05/01/2026 17:40] namibj DDR to the rescue? [05/02/2026 02:31] mithro_ FYI - The diagrams are at https://github.com/mithro/wafer-space-die-pad-diagrams/tree/main/diagrams {Embed} https://github.com/mithro/wafer-space-die-pad-diagrams/tree/main/diagrams wafer-space-die-pad-diagrams/diagrams at main ยท mithro/wafer-space... Contribute to mithro/wafer-space-die-pad-diagrams development by creating an account on GitHub. 2026-05_media/wafer-space-die-pad-diagrams-E3ED5 [05/02/2026 02:33] mithro_ You have a ULPI USB interface? [05/02/2026 02:36] mithro_ At the current time packaging is a large part of the cost here and packaging is driven up by the number of IO pins. IO pads also take up quite a bit of die space. Hence figuring out options for SERDES and other ways to reduce pin count is something I'm very interested in. [05/02/2026 06:19] ravenslofty Yes [05/02/2026 06:24] mithro_ @Lofty - Cool! I think having a bunch of proven USB connectivity solutions would be a huge gain for community. [05/02/2026 06:24] mithro_ @tnt also had some type of USB interface on the Tiny Tapeout chip. [05/02/2026 06:26] ravenslofty I knew I was going to be bandwidth hungry but also needed some kind of standard communication interface; at one point the plan was to have the chip be its own PHY and run at Full Speed, but then it was suggested that I could use ULPI and aim for Hi Speed instead. [05/02/2026 06:29] mithro_ FWIW - The original design doc for Caravel had it providing a high speed interface between your tape out and a computer and a whole bunch of "virtual" digital and analog pins that could be queried via virtual logic analyser / virtual oscilliscope so the limited number of pins that we could provide cost effectively was less of an impact, but that never quite happened. [05/02/2026 06:30] mithro_ I'm still interested in reaching that type of goal. [05/02/2026 18:19] namibj If you have a little space (it's the smallest analog tile on ttsky26a, but you'd probably want higher current output drivers if they don't have to go through an analog mux), two analog pads, and some tt-style Mux'd digital access, and would give a functioning one to @azonenberg for characterization, I'd put considerable effort into porting my currently-in-progress ttsky26a submission to gf180mcud in time for the wafer.space Run2 GDS deadline. (I hope to assume correctly that there is deep-nwell and the capability for placing `nmos_03v3_nvt` devices with raised bulk in said deep-nwell. And decent models of those in the region just around/above the (effective) threshold. With those "requirements" I'd see no reason why my ttsky26a submission wouldn't be readily portable to Run2. At least for short channels (no backplane or multi-meter Twinax!) an RX design might be possible to attempt before the Run2 deadline.) I'll try my best to get a parasitics-extraction simulation of the VCO core done today so we'd know where things stand both with the VCO itself as well as with an SDR latch fast enough to do a DIV2 on the VCO. No inductors involved. [05/02/2026 18:47] 246tnt So has anyone tested their COB package yet ? [05/02/2026 18:48] tholin I will on tuesday [05/02/2026 18:49] tholin Or... wednesday? The package got delayed? [05/02/2026 18:49] tholin Thatโ€™s not good, Iโ€™m not home wednesday [05/02/2026 18:50] tholin Did the COBs get shipped in an envelope (like the dies) or package? [05/02/2026 19:11] simi150500 envelope [05/02/2026 19:11] tholin Oh, very good. Lets hope it fits in my mailbox. {Reactions} ๐Ÿ‘ [05/02/2026 21:37] namibj making you have a mailbox that will fit them (if you ask nicely enough you can probably get fairly good dimensins) could allow you to reduce the need for hope/luck. (I should get me a mailbox that can fit German Maxibrief; C4 (or B4?) at the 3?5?cm thickness, or at least letters of full size (non-folded) without substantial bending....) [05/02/2026 21:38] tholin The envelope with the dies fit [05/02/2026 21:38] tholin So should be fine [05/02/2026 21:41] namibj (I say this because the COBs are from what I could see at breaking tap's post, slabs of PCB as they were processed at the bond house, not individualized or like the dies, taped.) [05/03/2026 03:26] anfroholic @Tim 'mithro' Ansell do we know the formfactor the COB were send in? Envelope or box? [05/03/2026 03:45] mithro_ @Andrew Wingate - Smaller padded envelope inside a non-padded fedex envelope. {Reactions} ๐Ÿ’ฏ (2) [05/03/2026 05:18] mithro_ @Andrew Wingate - BTW Did you share the bond diagrams you are generating here? [05/03/2026 05:39] anfroholic I only shared Breaking Taps' version. https://discord.com/channels/1361349522684510449/1408134567491145728/1499326875657306113 I can share more if you like. [05/04/2026 07:19] 246tnt @Greg Does the arrow sticker on the picture mean you found an issue with that particular chip ? [05/05/2026 15:26] tholin I donโ€™t know how I failed to notice that my dies are upside-down when I looked closely at this. Confirmation bias, probably. [05/05/2026 15:40] 246tnt I'm looking at https://discord.com/channels/1361349522684510449/1408134567491145728/1495357823314563143 and the pad 0 indicator (which is the one where QR code is on the dies) is on the side of the silk `Uxx` markers. [05/05/2026 15:45] 246tnt Ah yeah, I see. In the repo for the COB PCB the board orientation is not the same as the GDS orientation. https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/blob/main/74pad-70pin-mezzanine/wirebonding/wirebonding.png [05/05/2026 16:11] tholin I simply expected the top of the GDSII layout to be aligned with the top of the PCB layout, and was never informed otherwise Even in that wireponding.png view, you have to squint to see where the QR Code and logo are. [05/06/2026 16:22] meinhard How are Vcore, VIO, and Vaux currently/in future used? The cob module routes them separately but they seem to be low-ohmically connected. [05/06/2026 16:46] mole99 In the (very) near future, you will be able to have separate voltage domains in your chip by using the wafer.space template. The foundry-provided pads short the core and I/O domain on purpose. This will be possible thanks to Tim's 3.3/5V I/O cells, which have a level shifter between core and I/O domain and keep both domains properly separated in the power/ground pads. As for Vaux, the idea is to provide another voltage domain directly to the core. {Reactions} ๐Ÿ‘ ๐Ÿ˜ฎ [05/06/2026 18:33] meinhard Great, thanks for the info @Leo Moser (mole99) {Reactions} ๐Ÿ‘ [05/07/2026 13:31] greg.hashtag.9468 Yes. that particular one has a lifted bondwire. Found just with a visual inspection. Threw a QC flag so I didn't forget about it. [05/07/2026 13:35] 246tnt Interesting. I couldn't really tell from the image. [05/10/2026 02:22] mithro_ @tnt - FWIW @Lauri has been contracted to do an automated tester base around the reverse biasing the ESD diodes like you suggested. [05/17/2026 16:20] polyfractal @Andrew Wingate question about the mezzanine breakout board. I'm looking at the die and COB pinout, Pad0 is top right on the die (by QR code) and bonds to top-right pad on COB (by wafer.space logo). So I'm assuming it drops down a via and goes to the right side of the mezzanine connector (while still at the die from above). But the mezzanine breakout board lists Pad0 on the left side and the silkscreen has a dot on the top-left pin too. I _think_ Pad0 will drop down onto the right side of the breakout board but thought I'd ping first before I started releasing magic smoke ๐Ÿ™‚ {Attachments} 2026-05_media/image-D3FF9.png 2026-05_media/image-86799.png 2026-05_media/image-6D220.png [05/17/2026 16:26] 246tnt Why not check the cob pcb directly? [05/17/2026 16:37] anfroholic Hey @BreakingTaps Yeah, sorry about how this all looks, nothing ever wanted to play nice with the way the pads were laid out and the way kicad wants things. I have been talking with @Tim 'mithro' Ansell and @Leo Moser (mole99) about changing how we have our orientations and pin/pad orderings so things make better sense here and across the different sizes. The first picture is how it would look if you were looking 'through' the cob at the pinout. The other one is how it would look if you had it backwards and were looking at the mezzanine connector directly from the back. Hope that makes sense, also I just arrived home from Shenzhen in what turned into a 4 day journey home, so please reverify yourself please. Hope this helps {Attachments} 2026-05_media/image-057FA.png 2026-05_media/image-933EF.png [05/17/2026 16:38] anfroholic And yes, pad 0 is the one by the qr code [05/17/2026 16:45] polyfractal Oh yikes, four day travel home apologies for the ping! ๐Ÿ˜ฑ Glad you made it, I imagine things did not go quite to plan. Cheers for the help! [05/17/2026 16:45] polyfractal I've only used kicad like twice, but this might be the sign that it's time to learn ๐Ÿ™‚ [05/17/2026 16:47] anfroholic No need for apologies! Can't wait to see you bring it up. Don't hesitate ever to message, I could be in any timezone ;) {Reactions} โค๏ธ [05/17/2026 17:05] mithro_ @psychogenic has some great YouTube videos on using KiCAD ๐Ÿ™‚ {Reactions} ๐Ÿ’ฏ ๐Ÿ‘€ [05/18/2026 15:54] mithro_ @Lauri seems to have made some great progress on the wire bond connectivity tester! {Reactions} ๐Ÿ‘ [05/18/2026 22:17] mithro_ @Lauri - The number of pads @ https://mithro.github.io/gf180mcu-project-template/ are now correct for the 1x1 default. {Reactions} ๐Ÿ‘ [05/20/2026 15:20] zorin1384 Is there anyone looking for a developer? [05/20/2026 22:35] rebelmike I've been having some luck routing the tall thin one (0p5x1) by having the die at 45 degrees: {Attachments} 2026-05_media/image-9F41B.png {Reactions} ๐Ÿ’œ [05/20/2026 22:35] anfroholic That's interesting [05/20/2026 22:37] rebelmike Ended up breaking compatibility with some of the TinyQV pins, but none of the important ones - so bidir[27:0], in[1:0], clk and rst_n all match the 1x1 [05/20/2026 22:38] anfroholic Oh, is this one also only 2 layers? [05/20/2026 22:38] rebelmike Yeah [05/20/2026 22:39] anfroholic Would you mind setting your min trace spacing to .103mm please. The last boards I had to change a bit as the boardhouse complained some parts were <.1mm I don't think you did anything wrong. I checked and DRC was clean... [05/20/2026 22:39] rebelmike I guess the one thing I haven't considered yet is whether I can connect all the grounds, but hopefully I'll work something out ๐Ÿ˜„ {Reactions} ๐Ÿ˜‚ [05/20/2026 22:39] anfroholic haha, if it has to be 4 I don't think that's the end of the world, and if that's the case you can also disregard the previous statement. [05/20/2026 22:40] anfroholic 4layer spec is .09 so we're all clear there. [05/20/2026 22:41] rebelmike Will do. Also for the last one I had hole to hole 0.25mm, but I double checked the JLC rules and they are 0.2 so I tuned that down to 0.2, does that sound ok? Maybe should put a safety fudge on that too? [05/20/2026 22:41] anfroholic Wouldn't hurt. Again, I have no idea why they failed us. let me get the pic, 1 sec [05/20/2026 22:43] anfroholic This was what they sent us. {Attachments} 2026-05_media/ADKq_NYBZIQX9_SJ7-7V5ApjeDTOvFztbDKtXYYCXW-DD362.png [05/20/2026 22:44] rebelmike Hmm, was the problem via to track? [05/20/2026 22:44] anfroholic 4 layer is also an easy fix. Also I have no idea, there are arrows everywhere it seems ๐Ÿคฃ {Reactions} ๐Ÿ˜† [05/20/2026 22:45] anfroholic > Hi there, > > Sorry to bother you, but we'd like to confirm with you an issue found when engineer making production file of your PCB order. > > The spacing between traces is smaller than 0.1mm which is not enough to proceed, could we help you cancel this order? [05/20/2026 22:46] rebelmike Weird, maybe some unit conversion caused some rounding issue? Anyway, I'll go up to 0.103 - I've got a bunch of tightly packed traces but hopefully won't take too long to wiggle them apart! [05/20/2026 22:50] rebelmike Cool, and good to know that 4 layer isn't a major issue - if we end up trying to do custom CoBs to match important pins on all the Racquet and TinyQV designs then routing might get even more fun! [05/20/2026 22:53] rebelmike Anyway - I need to call it a night - I've pushed my WIP to https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev if you want to take a look {Embed} https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev GitHub - MichaelBell/chip-on-board-wire-bonded-pcbs at half-slot-dev Wire bonded chip on board PCB designs. Contribute to MichaelBell/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub. [05/20/2026 22:53] anfroholic Thanks and goodnight [05/20/2026 23:03] namibj Are you doing JLC? If so, I'd be surprised why you weren't just going for 4L in the first place. [05/20/2026 23:12] anfroholic We are. That's why I was saying that as well. It's not much difference in price [05/20/2026 23:13] namibj Yeah 4L for signal integrity! [05/20/2026 23:13] anfroholic That as well [05/21/2026 03:04] namibj In the interest of possibly understanding safety margins that were shown to not be that large by Tholin's DAC's OpAmps, do we have material datasheet information or enough detail that I could dig such up for the COBs? Notably, thermal expansion behavior of the board; how the chip is attached to the board; what the goop is that's covering the front of the die. [05/21/2026 21:46] rebelmike So I was thinking - if the plan is to do custom CoB PCBs for TinyQV and the other run 1 half slot designs, then why are we trying to match the pinout for the default template on the generic half slot CoBs? It would be better just to do the natural pinout and then fix the templates, rather than doing more complex than necessary routing and then locking that in for future runs. It would also make sense to update all the CoBs to 4 layer for better signal integrity if the cost difference is negligible. That does obviously require the generic CoBs are completed reasonably quickly so that the template can be updated in plenty of time for the run 2 designs. But I wouldn't suggest moving any of the power pads, clock or reset, and beyond that it is likely that pinout matching only matters if people are submitting the same design at different slot sizes, or expecting a common motherboard to work between different slot sizes on the basis of using pins with the same name in the template. Thoughts? [05/21/2026 21:48] anfroholic I've been speaking with @Tim 'mithro' Ansell and have been wanting to change things about the layout and the standard template and fix things at the beginning so it's harmonized across the sizes from the start. [05/21/2026 21:51] rebelmike Cool, it probably wouldn't take long to work out what the natural pad order would be and adjust the default template, even if the routing isn't actually done at that point. I know @Leo Moser (mole99) is planning to push a significant template update soon so if that is the direction maybe getting it done before that goes out would be a good idea {Reactions} ๐Ÿ‘ [05/22/2026 01:20] mithro_ I'm sure a professional packaging house will happily provide you with all these details if you are willing to order at least 1 million units a month. For $1.50 USD for <1000 units getting things like data sheets is pretty impossible most of the time. [05/22/2026 06:22] mole99 I agree, we should probably do all of the major changes now, so people only need to migrate once. @Andrew Wingate we should also change the pin order of the die to match the CoB, so that it doesn't need to be turned upside down. This should help reduce the confusion around the pinout, too. [05/22/2026 06:42] 246tnt Why not just rotate the CoB PCB by 180 deg ... ? [05/22/2026 06:49] 246tnt The pin number themselves already match, it's just on the PCB version / footprint, it was rotated so the first is on the top right instead of bottom left ... [05/22/2026 08:13] mole99 I thought there was a reason downstream why that isn't easily possible. @Andrew Wingate what was the reason again for rotating the die? Perhaps we should just change the PCB then. In any case, it should be consistent. [05/22/2026 18:57] anfroholic @tnt @Leo Moser (mole99) Just rotating won't fix the underlying problem. We should strive to harmonize default across the different die sizes. If we follow something like my diagrams here, you could design for any size die and still get a cob that matches all three (or four if the 1/4 slot follows) I prefer the fiducial to be up top because it follows convention {Attachments} 2026-05_media/image-C9BE3.png [05/22/2026 18:59] tholin I think the thing that made it confusing is that the die has a wafer.space logo on it and the PCB has a waver.space logo on it, but they are on *opposite corners* from each other [05/22/2026 19:00] tholin Instead of it being used as a alignment marker [05/22/2026 19:01] anfroholic Agreed that did not help. Not sure how it's getting announced, but if you want to have the COB 3 corners will be used by the defaults. Qr code, ws logo, blank space. The Qr and the blank will be in opposing corners [05/22/2026 19:30] 246tnt @Andrew Wingate The current COB footprint on the PCB has the pad 0 in the top right, not top left ... so if you rotate it 180 it's fine and aligned with the die. [05/22/2026 19:30] anfroholic That is correct [05/22/2026 19:31] 246tnt That was the main issue in assmbly ... people expected the die to be placed in the same way it was visible in the GDS. [05/22/2026 19:34] anfroholic I believe what we have here is an [x y problem](https://en.wikipedia.org/wiki/XY_problem) To me, I think harmonizing across the die sizes is the bigger issue. If you're changing that, then also change the position of the fiducial so it cannot be confused. {Embed} https://en.wikipedia.org/wiki/XY_problem XY problem The XY problem is a communication problem encountered in help desk, technical support, software engineering, or customer service situations where the question is about an end user's attempted solution (X) rather than the root problem itself (Y). The XY problem obscures the real issues and may even introduce secondary problems that lead to miscom... [05/23/2026 17:05] rebelmike I think there are just two independent issues that should be addressed at the same time: - The CoB layout for half and quarter slots isn't finalised (and wasn't known when run 1 designs were done), so projects in different size slots can't match their pinouts. Once the layout is known it would make sense to harmonize the default template (but most people will customize that anyway, so the important thing is knowing the mapping). - The wafer space logos are in different places on the board and the chip, which is confusing. The proposal seems to be to change both board and template to have the logo (and therefore pin 1) in the top left, is that correct? Obviously everyone will need to update their run 2 projects if that change is made. [05/23/2026 18:12] anfroholic Agreed, and thanks for the work you've done with the half slot dies. And to be clear, a lot of the changes I'm requesting are still just my opinion. That said, having worked with a number of the downstream effects, someday we're likely to want to make changes. Harmonizing the template across sizes will help with whatever next version of cob we may introduce, if people want to harmonize across different dip like packages, this would be easier. Unless I'm mistaken, I think we collectively have enough information to make some better decisions across the board. And doing so sooner than later would be better. {Reactions} ๐Ÿ‘ [05/23/2026 18:18] anfroholic Also of note, any of these propositions are _only_ for people who are looking to get the standard COB packaging. Other than that, anyone's still free to do whatever they like. [05/23/2026 18:20] rebelmike On the half slot CoBs, Iโ€™ve now got distracted by a possible run 2 silicon project, but I could potentially do some more on those. [05/23/2026 18:21] anfroholic The first panels of the p5x1 version should be back from the board house in the next few days if I understand correctly {Reactions} ๐Ÿ‘ [05/23/2026 18:25] rebelmike CoB work items I'm aware I could look at: - Make a simplified version of the 1x0p5 CoB, and also going up to 4 layers. That would become the standard one going forwards - Have another go at the 0p5x1 - this time going for the simplest routing, and hence probably just having the chip in the obvious "upright" position rather than diagonal. Again change to 4 layers. - Create run 1 TinyQV specific 1x0p5, 0p5x1 (and eventually 0p5x0p5) CoBs that match clk, SPI, UART to the pinout of the 1x1 GD03 Racquet project. [05/23/2026 18:27] rebelmike Then there's: - Create a motherboard against that pinout that could be used by TinyQV or Racquet with the custom CoB - And also make a TinyQV motherboard for the original 1x0p5 CoB, if I'm likely to receive any chips bonded to it ๐Ÿ™‚ [05/23/2026 18:28] rebelmike I would ideally like to get my hands on a TinyQV board a little before the run 2 deadline as I may be doing a revision so it would be good to know if anything didn't work [05/23/2026 18:33] anfroholic > And also make a TinyQV motherboard for the original 1x0p5 CoB, if I'm likely to receive any chips bonded to it As far as I understand, this is definitely the plan. I can't imagine it's not. I'm not in China anymore so am a bit more detached now. I would bet something gets sent to you in about a week or two. [05/23/2026 18:36] rebelmike Awesome! There's two copies of TinyQV in this size slot so even if Tim would like a bunch in a custom CoB eventually there should be loads left still. I'll put together a quick motherboard based on the pinout on the existing CoB so I have something to test with. {Reactions} ๐Ÿ’œ [05/23/2026 19:17] rebelmike Just to double check, is this the correct part for the mating connector? https://www.lcsc.com/product-detail/C19089292.html {Embed} https://www.lcsc.com/product-detail/C19089292.html HC-PBB40C-70DS-0.4V-3.0-02 | HCTL | Price | In Stock | LCSC Electro... HC-PBB40C-70DS-0.4V-3.0-02 by HCTL - In-stock components at LCSC. Price from $0.3911. Free access HC-PBB40C-70DS-0.4V-3.0-02 datasheet, Package, pinout diagrams, and BOM tools. 2026-05_media/20240229_HCTL-HC-PBB40C-70DS-0-4V-3-0-02_C-A7BFB.jpg [05/23/2026 19:17] rebelmike The link from the https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/ readme is broken (maybe the part number has changed?) [05/23/2026 19:18] anfroholic That is correct. Keep in mind there are a number of different heights if that is of concern, and there are also other compatible brands as well. {Reactions} ๐Ÿ‘ [05/23/2026 19:20] anfroholic The link has been fixed. Thanks {Reactions} ๐Ÿ‘ [05/23/2026 23:53] rebelmike Doh. Just finished routing my board. For some reason at that point I decided to double check that the pinout of the mezzanine connector was correct. And it's not - the pins on the connector in the motherboards project which I grabbed the footprint from are flipped compared to the CoB! That doesn't matter for those simple breakouts because they just expose all the pins. Incidentally I think that means the pin 1 marking on those simple breakout motherboards is actually against pin 70. [05/24/2026 08:14] rebelmike Ah, this is the same thing that @BreakingTaps spotted last week! {Reactions} ๐Ÿซ  [05/24/2026 10:55] mole99 Started a thread. [05/24/2026 17:48] anfroholic Hey @Leo Moser (mole99) stuff seems to get lost in threads on discord. For starters, I don't think any of this 'should' happen for run2. I think it's too late for that. > I'm not exactly sure what your diagram is showing? I just decided to make a rough thing to illustrate. @RebelMike you could probably imagine a ring of vias that do whatever on the bottom side, but all route cleanly on the top. > I agree that we should harmonize what we can between the different slots sizes. What are your plans with regards to matching the pinout? If we want to keep that many pins on all the half slots and drop 2 from the 1x1 we end up with them all being identical. I don't know what this means in reality, but if someone wanted to prototype on a half slot, then move to a larger size, the pin/padout stays identical. > PS: Looking at the CoB PCB for the 1x1 slot, pin 1 of the mezzanine connector seems to be in the top right corner rather than the top left. Why is that the case? KiCads generic connector library and most packages and connectors in general have pin1 in the top left. I would prefer, if someone were to take a generic mezzanine connector and use the footprint provided by the manufacturer, for pin1 to line up. There's already a lot of confusion when trying to go through all these maps to add one more translation. {Attachments} 2026-05_media/harmonized_slot_1x1-7F68B.png 2026-05_media/harmonized_slot_1x0p5-AB264.png 2026-05_media/harmonized_slot_0p5x1-C10AE.png [05/24/2026 18:17] 246tnt But connectors is on the bottom of the PCB, opposite of die. And then the connector on the "user side" is also swapped because it's the other side of the connection ... they can't be all top left pin 1 footprint, at some point swap needs to occur ... [05/24/2026 18:20] anfroholic Agreed, when mentioning the connector above, I was referring to the connector a user would be sourcing (on their motherboard). The important one in my mind is the final connector and the die itself to match. [05/24/2026 18:37] 246tnt But the "manufacturer footprint" argument doesn't hold really. If you look at the kicad library ( in the Hirose library for DF12 that's the closest I have installed ), the `DS` side connector which would be the "user side" , they standardized indeed on pin 1 top left ... with the connector horizontal. Which means top right if you put it vertically ( or bottom left ) ... [05/24/2026 18:51] anfroholic Whatever, I'm not religious about this. Seems like others are. I also tend to make and throw a bunch of stuff against the wall to see what sticks. More to the point of harmonizing. There is an error in my pictures from the last post. I am reposting more correct versions. I have also created an example slot_size.yaml thing. I am not sure how many people will be designing for multiple slot sizes, or how difficult that is. @RebelMike can maybe speak to that. In the spirit of making more things, I propose a config that has a different shape. There is a single list of pads that doesn't change between slot sizes. {Attachments} 2026-05_media/harmonized_slot_0p5x1-81F56.png 2026-05_media/harmonized_slot_1x0p5-8229F.png 2026-05_media/harmonized_slot_1x1-1ECF6.png 2026-05_media/example_padring_0p5x1-1842D.yaml 2026-05_media/example_padring_1x0p5-056A3.yaml 2026-05_media/example_padring_1x1-D7C00.yaml [05/24/2026 18:52] anfroholic And for the record I am aware this obscures a starting pad even further [05/24/2026 19:25] namibj IMO what needs to be clear and uniform across all 3 slabs of multilayer routing is that there's exactly one clear orienting corner, and they all line up when assembled correctly. Die, COB, motherboard's socket area. {Reactions} ๐Ÿ‘ (2) [05/24/2026 19:28] namibj That's easy to verify when looking at a layout and picking like 3-ish nets to highlight and visually check. The top surface of all 3 is the same "up". {Reactions} ๐Ÿ‘ (2) [05/24/2026 19:30] namibj (in the sense of surface-normal-vector direction) [05/24/2026 20:06] rebelmike I was assuming power pads would stay where they were and this was simply an exercise in renaming the signal pads in the default template on the half (and quarter) slots. That basically has no implications except for helping make the CoB pinout clearer as there would be a single mapping default template -> pins, which projects could compare their renamed pins against. But for run 3 obviously bigger changes could be considered - I'm not clear on what the implications of removing two power pads from the 1x1 pad ring would be. [05/24/2026 20:20] namibj Don't remove too many power pads, at least if we have a way to not fry chips as much as the avalon Run1 DACs are doing. [05/24/2026 20:20] namibj larger chip more consumption [05/24/2026 20:21] rebelmike My thoughts: - The wafer space logos should be in the same position as it's the obvious marker to align in assembly (I'd weakly suggest top right as aesthetically it looks most pleasing there - Andrew and Leo both put it there independently AFAICT) - this doesn't necessarily need to mean "pin 1". - To allow that without users having to change their run 2 designs, the CoB pinout should be changed (this would likely end up ~a 180 degree rotation on the current pinout, and maybe if it could be exactly that that would leave some compatibility between run 1 and run 2). - The project pad -> mezzanine pin mapping should be clearly documented, with reference to the pad names in the default template and the pin names on the mezzanine footprint for the user's motherboard. - The signal (and VDD?) pins on the default templates should be harmonized as much as possible, so the above documentation applies to all slot sizes Ideally that should be done for run 2, because the current state is a source of confusion and mistakes. [05/24/2026 20:24] rebelmike On the pin types in the templates, I suspect it would make sense to keep some analog and input ones to highlight their existence in the template, rather than just making everything bidir. My principle of least change was suggesting make everything match the current 1x1 but that does have quite a large number of dedicated inputs [05/24/2026 20:28] anfroholic Think of all these as conceptual models rather than genuine proposals. More power pins are perfectly acceptable. An overarching goal expressed by @Tim 'mithro' Ansell is to look for ways to reduce cost in efforts towards accessibility. This likely means moving away from the mezzanine all together, and taking any decoupling caps with it, since assembly is no longer an operation we're doing. No caps means more pins can be used for whatever purpose as they all become generic wires. [05/24/2026 20:29] namibj Yeah it's a good top right corner "arrow" [05/24/2026 20:30] namibj {Attachments} 2026-05_media/image-941E6.png [05/24/2026 20:30] namibj qr code lacks coarse structure contrast [05/24/2026 20:31] namibj W.S logo or alternatively (if for some reason that has to not be there) an Intel LGA style triangle should be strongly recommended. [05/24/2026 20:32] namibj (The QR would work if the other corners were blank, but they aren't.) [05/24/2026 20:36] anfroholic I think all that sounds reasonable. > The project pad -> mezzanine pin mapping should be clearly documented, with reference to the pad names in the default template and the pin names on the mezzanine footprint for the user's motherboard. I'm finally getting settled as I get home and plan to work on cleaning the repo with the current COB and better document the motherboard. I think that will take away most of the confusion. > The wafer space logos should be in the same position as it's the obvious marker to align in assembly (I'd weakly suggest top right as aesthetically it looks most pleasing there - Andrew and Leo both put it there independently AFAICT) - this doesn't necessarily need to mean "pin 1". The one request I did have, is whatever corner we are using as 'fiducial' has the opposing corner blank. This could happen this run, or not. > To allow that without users having to change their run 2 designs, the CoB pinout should be changed (this would likely end up ~a 180 degree rotation on the current pinout, and maybe if it could be exactly that that would leave some compatibility between run 1 and run 2). I don't understand this one fully? Basically rotate all the copper 180? That would do it? (negating changes to the schematic) > The signal (and VDD?) pins on the default templates should be harmonized as much as possible, so the above documentation applies to all slot sizes This is a run3 thing? [05/24/2026 20:39] anfroholic > The signal (and VDD?) pins on the default templates should be harmonized as much as possible, so the above documentation applies to all slot sizes I think I see. When making all this I did not have that info. I've been filling in this spreadsheet as I got more info https://docs.google.com/spreadsheets/d/1pI2BAEWEexXcXN3vah3SR85zPIV6eAXPGXc2bcvoSGU/edit?gid=0#gid=0 You're saying to use the info in the `config.yaml` column? {Embed} https://docs.google.com/spreadsheets/d/1pI2BAEWEexXcXN3vah3SR85zPIV6eAXPGXc2bcvoSGU/edit?gid=0 waferspace GF180 standard 74 pad padframe V1 2026-05_media/AHkbwyLZAovCtMJvwciifhE2XeF27uR8LjNtmsKAVg-B5A78 [05/24/2026 20:43] rebelmike > The one request I did have, is whatever corner we are using as 'fiducial' has the opposing corner blank. This could happen this run, or not. The location is specified in the project's config, but I assume is validated by the submission system, so changing it and then advising people of the change should be possible? > Basically rotate all the copper 180? That would do it? (negating changes to the schematic) Yeah I think rotating everything through 180 but leaving the logo where it is would resolve it. > You're saying to use the info in the config.yaml column? Yes - while users will rename their pins, they will have started from this setup so it seems the most meaningful thing to me. Maybe I'm putting too much weight on it though [05/24/2026 20:45] anfroholic Can you explain the reason they may be called `bidir\\[0\\].pad` and `inputs\\[0\\].pad` instead of something more generic if it's just overwritten anyways? [05/24/2026 20:47] rebelmike This is what's specified in https://github.com/wafer-space/gf180mcu-project-template/blob/main/librelane/slots/slot_1x1.yaml And the number of bidirs / analog / inputs match the defines in https://github.com/wafer-space/gf180mcu-project-template/blob/main/src/slot_defines.svh [05/24/2026 20:49] rebelmike Users may well change those to match their needs, but given wafer space is providing both the project template and the CoB, referring to things by those names seems like it should make sense to people {Reactions} ๐Ÿ‘ [05/24/2026 20:52] rebelmike In my case, I was short on time and also didn't know what slot size you might have going spare, so I just fitted my design in to the template without changing any of the pad names. Then you had spare slots of all half and quarter sizes so all 3 got produced! That's what led to me wishing that the default pinout was harmonized back in run 1. That's probably a pretty unique circumstance though so I think going forwards its more about documentation, but it would also reduce surprises if you do switch which slot you're targetting. [05/24/2026 20:57] anfroholic I'm going to go out on a limb and say I don't think switching slot sizes will be all that uncommon in the future. More or less I think things are pretty entrenched as far as run1 goes. I'll try to make the changes listed above. I would like to keep the conversation alive about run3 though. Thanks for the input {Reactions} ๐Ÿ‘ [05/24/2026 21:12] namibj oh, hmmmmm..... @BreakingTaps any hope for the idea of using ACF and DRC-pushed FPC (JLC just about lets you do 102 um pitch on the 5$ special)? Or is that too high resistance/would need fancy surface treatment on the die to connect to the aluminium topmetal? I'd expect AOI to reject even up to half the FPC production to be sufficiently practical to work from that POV; but it's not easy to find out if the commodity ACF would have sufficient performance to do the task of W.S default/bargain fan-out. It is my understanding that the traces are on top of the core and the lack of fine-pitch coverlay/soldermask would imply that these are bare metal strips on an underlying flat polyimide core; so that might be enough "bump"? It's about 12um thick there. [05/25/2026 00:02] namibj Ok I'll draw up a standard COB pinout FPC for that tomorrow. This.... _might just work._ [05/25/2026 00:03] anfroholic What is this? [05/25/2026 00:09] namibj https://www.youtube.com/watch?v=0HZ35CyHVxQ https://web.archive.org/web/20190708182030/https://fsrkj.com/upfiles/201712/22/af0aa1f1cb2886b6f.pdf It's on aliexpress for like 7 USD a roll; seems to not be hard to get one's hands on, and it's just `190ยฑ10 C` for 10 s at 2 MPa via a hard-ish silicone sheet (200~300 um they say, shore 70+) with a thn teflon sheet (25~50 um) between that and the FPC, pressing the contact strip area down using a sufficciently solid anvil underneath to not harm the more-fragile die (or, in the original case, the LCD's glass; it works for dies too, though, "just" not well on aluminium at least with that standard metallurgy) {Embed} Breaking Taps https://www.youtube.com/watch?v=0HZ35CyHVxQ The Microspheres Hiding in your Phone's Screen The first 1,000 people to use the link will get a 1 month free trial of Skillshare https://skl.sh/breakingtaps07231 Watch this video ad free on Nebula: https://nebula.tv/videos/breakingtaps-conducting-electricity-in-only-one-dimension ------------------------------------------------------- Today we're looking at Anisotropic Conductive Film (A... 2026-05_media/maxresdefault-4DA13.jpg [05/25/2026 00:16] anfroholic I've seen this video before. Super neat!! Good luck! [05/25/2026 00:18] namibj yeah same I remembered didn't even remember it was him but tbf, fits. [05/25/2026 17:42] polyfractal oh that's a fun idea! I'm not sure to be honest, might be dodgy for high frequency signals, but maybe fine for less demanding tasks? I dont actually have much experience with the stuff on real projects, just tearing down existing projects to get to the ACF for microscopy ๐Ÿ™‚ But yeah it's used all over for displays Could be a really clever way to get flipchip without needing the fab to bump for us! {Reactions} ๐Ÿ”ฅ [05/25/2026 18:52] namibj It's actually waaaay better for high frequency it's a bit resistive but I'm sure that's easy to tune away in a transceiver as we talk like a couple Ohm at the terminus. That 3mm bond wire at 1 GHz is already 12 ohm though... If you have any idea how to get some test dies receptive to the nickel spheres.... [05/25/2026 18:54] polyfractal ah interesting, why would more resistance help with higher frequency? I sorta assumed you'd want the shortest, most conductive path possible? [05/25/2026 18:55] polyfractal our topmetal is aluminum right? I just skimmed that old video of mine and they used Al on the glass connector side. So it was Al -> ACF -> Ni/P coated Cu fpc [05/25/2026 18:56] anfroholic As far as I understand, yes, it's aluminum. {Reactions} ๐Ÿ‘ [05/25/2026 19:08] fossify_37988 It's easier to control resonances with slight dampening. You lose a bit of Q but you get a more consistent response {Reactions} ๐Ÿ‘ (2) [05/25/2026 19:39] polyfractal gotcha, TIL! [05/26/2026 03:58] namibj It's got comparatively _zero_ inductance once you include the remaining parasitics. [05/26/2026 03:59] namibj Wait they they.... They did Al straight to the ACF??? I'll get you a JLC special FPC layout/pinout for your die before the weekend if you'd be interested in trying. [05/26/2026 04:05] namibj Well it's more that you can tune the launch impedance a bit anyways once it matters and that'll easily cover the spread in series resistance from the ACF. Like you already need the structures in the PA (yeah it's digital but it's still a power amplifier, with tuned distortion, and sometimes integrally fused modulator if the output itself is naturally clocked instead of being a second stage after the clocked stage) and a bit more tuning range to cover increased stacking of variance is not really expensive at that point. So therefore you might as well just enjoy the much lower inductance. [05/26/2026 04:11] namibj If you have any special wishes on that provide a schematic. I'd plan for having the mezzanine connector off the side so you could bend it and have the entire thing barely taller/thicker than the original cob, but now with the die backside exposed to attach a heatsink. I'd probably do it on Thursday early Berlin time; if that's too early I'd get to it approximately a week later (that's Germanys closest thing to a comiket this coming weekend I'll be running on fumes by the end). [05/26/2026 08:59] mithro_ What does ACF stand for? [05/26/2026 09:01] namibj https://discord.com/channels/1361349522684510449/1408134567491145728/1508260597412921375 [05/26/2026 09:01] mithro_ ACF is the tape stuff that @BreakingTaps is talking in the video you shared? [05/26/2026 09:01] namibj Yeah [05/26/2026 09:02] namibj It's what they use to bond to notably LCDs and other TFT-on-glass type active-matrix displays like OLED. [05/26/2026 09:03] namibj It's a 180~190C for 2~10 seconds thermoset epoxy used with about 2MPa pressure. [05/26/2026 14:28] polyfractal "Anisotropic Conductive Film" yep [05/26/2026 14:29] polyfractal At least for the glass-FPC interface, looks that way. Copper FPC pad on top, glass on bottom. Thin film of aluminum on glass side. (please excuse my shitty cross-section polishing I was in a rush ๐Ÿ˜„ ) Edit: also ignore the silver, iirc I sputtered a very thin layer on to help with charging on the glass {Attachments} 2026-05_media/Image_3_analysis_1_map_C_O_Al_Si_P_Ca_Ni_C-0E452.png {Reactions} ๐Ÿ˜ [05/27/2026 22:47] rebelmike I did a quick tweak to the generic breakout to make it 4 layer and label clk/rst/power/ground - don't know if this would be useful to anyone else: https://codeberg.org/rebelmike/ws-breakout {Embed} https://codeberg.org/rebelmike/ws-breakout ws-breakout 2026-05_media/summary-card-F05F8 {Reactions} ๐Ÿ‘ (2) [05/29/2026 04:40] mithro_ Cool! [05/30/2026 03:36] anfroholic Hey all, I've added and updated some of the readmes and moved all the run-1 stuff into it's own directory so we can keep things more organized moving forward. https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs This likely breaks any way for you to make pull requests Mike. *side note- this has the updated 1xp5 files that have the larger clearance.* @Tim 'mithro' Ansell @RebelMike {Embed} https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs GitHub - wafer-space/chip-on-board-wire-bonded-pcbs: Wire bonded ch... Wire bonded chip on board PCB designs. Contribute to wafer-space/chip-on-board-wire-bonded-pcbs development by creating an account on GitHub. 2026-05_media/chip-on-board-wire-bonded-pcbs-B6749 [05/30/2026 03:37] anfroholic Also updated the motherboards to have these as the symbols. {Attachments} 2026-05_media/0-8D144.png {Reactions} ๐ŸŽ‰ (2) ============================================================== Exported 239 message(s) ==============================================================